1. Field of the Invention
This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region to form the silicide on the gates which are in the periphery region and cell array region, and in the diffusion region which is in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.
2. Description of the Prior Art
An increment in device integrity makes the resistance of metal oxide semiconductor (MOS) device source/drain regions gradually climb up and almost equal to the resistance of MOS device channel. In order to reduce the sheet resistance of source/drain regions and to guarantee a complete shallow junction between metal and MOS device, the application of a xe2x80x9cSelf aligned Silicidexe2x80x9d process is gradually steeping into the very large scale integration (VLSI) fabrication of 0.5 micron (xcexcm) and below. This particular process is called xe2x80x9cSalicidexe2x80x9d for short.
In general, the titanium silicon is usually used in silicide. The titanium silicide is formed to use two sequence steps rapid thermal process. At first, referring to FIG. 1, a silicon substrate 10 is provided and a MOS device and a shallow trench isolation are formed thereon. The MOS device comprises a source/drain region 12 a gate region, and as well as a spacer 18 formed on the sidewalls of the gate region. This gate region comprises a gate oxide layer 14 and a polysilicon layer 16, then using the chemical vapor deposition technique or the magnetron direct current sputtering technique to deposit a titanium metal layer 20 over the MOS and the shallow trench isolation. The thickness of the titanium metal layer 20 is about more than 300 angstroms. Next, a rapid thermal process is performed, wherein part of the titanium metal layer will react with the silicon on the source/drain region and with the polysilicon of the gate region to form a titanium silicide layer. The thickness of this titanium silicide layer is about 600 to 700 angstroms. The structure of this titanium silicide layer is a metastable C-49 phase structure with higher resistivity. Referring to FIG. 2, the unreacted titanium metal and the remained titanium metal are removed by applying the RCA cleaning method. Therefore, the titanium silicide layer 22 is existed on top of the gate region and the source/drain region. Finally, a rapid thermal process is performed again to transform higher resistivity of the C-49 phase titanium silicide structure into lower resistivity of the C-54 phase titanium silicide structure.
In the deep sub-micron device fabrication, the decline of the device driving current that cause by parasitic seties resistance of source/drain can be avoided by siliciding the source/drain. The above can be accomplished by either using simple silicidation of source/drain or self-aligned silicidation, where self-aligned silicidation can accomplish the silicidations of source/drain and gate region at the same time.
In the present logic circuit, the silicide is also needed to be used to decrease the resistance of the conductive layer and to increase the qualities of the semiconductor device. In order to cooperate the operation of the logic circuit, the partial region of the logic circuit will not be formed with the silicide to prevent the leakage defects producing on the semiconductor device. In the traditional salicide process, the silicide is formed on the partial material, which need to form silicide, by using complex steps. In the present semiconductor process, the process efficiency is important. Therefore, the traditional complex steps, which need more time, are not suitable for the present semiconductor process.
In accordance with the above-mentioned invention backgrounds, the traditional method can not form the silicide in the partial region of the logic circuit quickly. The main object of the present invention is to decrease the resistance of the word line, which is in the cell array region and periphery region, by using an oxide layer to be the mask layer to form the silicide on the gates, which are in the cell array region and the periphery region, and in the diffusion region, which is in the periphery region successfully.
The second objective of this invention is to avoid the leakage defects occurring in the diffusion region, which is in the cell array region, by using an oxide layer to be the mask layer to form the silicide on the gates, which are in the cell array region and the periphery region, and in the diffusion region, which is in the periphery region successfully.
The third objective of this invention is to decrease the resistance of the periphery region by using an oxide layer to be the mask layer to form the silicide on the gates, which are in the cell array region and the periphery region, and in the diffusion region, which is in the periphery region successfully.
The fourth objective of this invention is to increase the quality of the semiconductor device by using an oxide layer to be the mask layer to form the silicide on the gates, which are in the cell array region and the periphery region, and in the diffusion region, which is in the periphery region successfully.
It is a further objective of this invention to increase the proceeding efficiency of the semiconductor device process by using an oxide layer to be the mask layer to form the silicide on the gates, which are in the cell array region and the periphery region, and in the diffusion region, which is in the periphery region successfully.
In according to the foregoing objectives, the present invention provides a method to decrease the resistance of the word line, which is in the cell array region and periphery region and to avoid the leakage defects occurring in the diffusion region, which is in the cell array region, by using an oxide layer to be the mask layer to form the silicide on the gates, which are in the cell array region and the periphery region, and in the diffusion region, which is in the periphery region successfully. The present invention method can also decrease the resistance of the periphery region. The present invention method can further increase the quality of the semiconductor device and increase the proceeding efficiency of the semiconductor device process.